1. Field of the Invention
The present invention relates to integrated circuits used for processing TV-type signals, i.e., composite signals representing picture lines including, for each line, a series of at least three signal portions: a portion of synchronization signal, a portion of suppression signal during which no picture information is transmitted, and the useful signal representing the information corresponding to the current picture line.
2. Discussion of the Related Art
FIG. 1 represents the standardized structure of a TV or composite video signal, as used not only for transmission of TV signals but also for video tape recorders and other picture display systems.
Assuming that the reference voltage is the voltage level Vsup transmitted during the information suppression phase. Then, the beginning of a line is marked with a synchronization signal which is a negative pulse having edges as sharp as possible and having a time duration of approximately 4.7 .mu.s. The suppression level Vsup is then emitted for approximately 5.3 .mu.s, the useful signal is emitted as a positive value above the suppression level for 52 .mu.s, and last the suppression level is re-emitted for approximately 2 .mu.s. The total transmission duration for a line is then approximately 64 .mu.s.
To operate a TV circuit, the line synchronization signal has to be extracted since it must control the line retrace of the screen scanning spot or, in matrix display systems, it must determine the addressing sequences of the various lines.
In the prior art, the circuits for extracting synchronization signals are generally fabricated in a bipolar integrated circuit technology. Such a technology is conventionally adapted to analog electronic circuits.
The principle of the most commonly used extracting circuits is illustrated in FIG. 2.
To provide a pulse at the occurrence of the synchronization interval, it is merely necessary to compare the composite video signal with an intermediate threshold value between the low voltage level Vsyn of the synchronization interval and the suppression voltage level Vsup. The most advantageous approach is to establish a threshold having a value (Vsup+Vsyn)/2. A comparator receiving the composite video signal and the threshold provides one pulse each time the video signal goes below the threshold, i.e., at the occurrence of the synchronization interval.
However, to achieve this purpose, this threshold must be established; it is therefore necessary to know the levels Vsup and Vsyn of the received signal. Such levels are not known beforehand. Thus, they must be determined from the signal received.
Moreover, when the composite video signal arrives, it is not referenced with respect to a reference voltage: it is a variable signal without any fixed d.c. value.
That is the reason why the following several steps are necessary: fixing a reference voltage of the composite signal, determining voltages Vsyn and Vsup with respect to this reference, establishing a threshold value (Vsyn+Vsup)/2, and comparing the aligned composite signal with this threshold.
In conventional circuits, the principle of which is represented in FIG. 2, the suppression level Vsup of the video signal is aligned with a reference voltage Vref.
To achieve this alignment, the composite video signal Sv is applied, through a first series capacitor C1, to an input terminal B1 of an integrated circuit. Signal Sv is offset by a value corresponding to the d.c. charge value of capacitor C1, to provide a signal Sv'. A first circuit stage, connected to terminal B1, then controls charging of capacitor C1 so that the offset signal Sv' has its mean suppression level Vsup exactly equal to a reference voltage Vref.
This alignment stage mainly includes a differential amplifier AD1, one input of which is connected to voltage Vref, and another input is connected to terminal B1. The comparator output controls either the activation of a charging current source SCc of capacitor C1, tending to increase the d.c. voltage across the capacitor, or the activation of a discharging current source SCd, tending to decrease this d.c. value. The ratio between the charging and discharging currents is such that charging of capacitor C1 is then automatically balanced said that the suppression voltage Vsup of signal Sv' is equal to Vref.
A second circuit stage then establishes a voltage Vsyn equal to the low voltage of the synchronization interval of signal Sv'. This second stage is simply a detector for detecting the negative peak value of signal Sv'. The circuit includes a capacitor C2 operable to store a d.c. charge representing level Vsyn. Capacitor C2 is connected between a terminal B2 and ground. A differential amplifier AD2 having a feedback loop including a diode D1 receives at one input signal Sv' and at the other input the voltage stored in capacitor C2. Diode D1 is operable to rapidly discharge the capacitor when the level of signal Sv' drops below the level stored in capacitor C2. As a result, the voltage level of capacitor C2 is continuously regulated to the value of the lowest level of signal Sv', i.e., Vsyn. A charging resistor R1 slowly recharges the capacitor when the low level of the synchronization interval tends to increase. Last, a follower stage (amplifier AD3 having a feedback loop to provide a unity gain) allows for exactly copying the voltage Vsyn present across the capacitor to apply it to a resistive divider. The follower stage avoids any spurious discharging of capacitor C2 through the divider resistors.
Last, the extracting circuit includes a third stage which is a stage comparing signal Sv' with a threshold equal to (Vsyn+Vsup)/2, i.e., which threshold is now equal to (Vsyn+Vref)/2. This third stage includes the above mentioned resistive divider, with two resistors R having the same value and serially connected between the output of the follower stage (at Vsyn) and the reference voltage Vref. A comparator (a differential amplifier AD4) receives at one input the signal Sv' and, at another input, the signal at tap T (the "medium" tap) of the resistive divider. The differential amplifier AD4 provides at its output S the synchronization signal extracted from the video signal.
In some applications, it is desirable to provide complex circuits for processing video signals, in which the circuit for extracting the synchronization is one component among others. For such circuits, it becomes necessary to use MOS technologies (i.e., technologies using insulated-gate field effect transistors). This may be due to the fact that the number of transistors is very high (for example, several tens or hundreds of thousand transistors); in this case, the requirement to decrease power consumption leads to the use of low power consumption technologies (technologies such as complementary MOS transistors). Another reason can be that most of the circuits to be fabricated are logic circuits instead of analog circuits because MOS technologies lend themselves to logic circuits more easily than bipolar technologies.
In these cases, if it is desired to avoid using dual (bipolar/MOS) technologies which are expensive, all the circuits must be fabricated with MOS transistors.
However, it has been noted that the circuit of FIG. 2, easily realizable in bipolar technology, becomes complex, cumbersome and unreliable when it is transposed into MOS technology.
Amongst the explanations that can be given, one reason is that it is not possible to easily provide reference voltage sources such as voltage Vref which must be identically applied to two different points of the circuit. Another reason is that differential amplifiers have an offset voltage substantially higher in MOS technology than in bipolar technology when simple amplifying circuits are used. However, these offset voltages directly affect the precision with which levels Vsyn and Vsup are established, and therefore on the threshold (Vsyn+Vsup)/2 and on the comparison of Sv' with this threshold. By way of example, the order of magnitude of the difference between Vsup and Vsyn is approximately 150-300 mV whereas the offset voltages of the MOS differential amplifiers commonly have a 10-20 mV dispersion. Last, the amplifier followers are more critical when fabricated in MOS technology (the risk for instability is higher).
One of the objects of the invention is to provide a circuit for extracting the synchronization signal from a composite video signal, capable of receiving the composite video signal and providing a synchronization pulse at the beginning of each line.